The present invention relates to a wiring structure in an integrated circuit device and to a method for forming the same. More particularly, it relates to a method for optimizing an amount of voltage drop in wiring.
In an integrated circuit represented by a digital circuit, logic gates including an AND gate and a NOR gate are used as elements for composing the circuit. A unit for organizing the logic gates into the circuit is termed a cell. In the digital circuit, cells having different functions in accordance with the types of the logic gates are prepared. By combining the different types of cells, the whole digital circuit acquires a necessary function.
In a typical digital circuit, a ground wiring layer and a power supply wiring layer are provided over a region in which a large number of cells are placed. The cells are arranged laterally such that the respective power supply lines of the cells are connected to each other and that the respective ground lines thereof are connected to each other. Hereinafter, a group of cells arranged laterally will be termed a cell raw.
The cells contain electronic elements required to compose the circuit, e.g., MOS transistors as components. For example, a CMOS inverter circuit contains a PMOS transistor and an NMOS transistor and has a power supply terminal connected to the power supply line of the cell, while having a ground terminal connected to the ground line of the cell. It is to be noted that a circuit in the present specification indicates a portion obtained by connecting electronic elements with a wire (in a broad sense) and does not indicate a closed circuit (in a narrow sense). For example, a CMOS inverter circuit indicates a circuit having a power supply terminal and a ground terminal which are not connected to the power supply line and the ground line, respectively.
FIG. 10 is a plan view showing the respective structures of a cell placement region, power supply lines, and ground lines in a conventional digital circuit composed of cells. As shown in the drawing, a plurality of cell rows 105x are aligned vertically in the cell placement region. Each of the cell rows is composed of a plurality of cells 105 arranged laterally. The cell placement region is defined by trunk power supply lines 107a and trunk ground lines 107b each extending vertically and by branch power supply lines 108a and branch ground lines 108b each extending laterally. Power supply voltages and ground voltages are supplied from the trunk power supply lines 107a and the trunk ground lines 107b on both sides of the cell placement region to the individual cells 105 via element power supply lines 106a and element ground lines 106b. The trunk power supply lines 107a and the trunk ground lines 107b are connected to the branch power supply lines 108a and the branch ground lines 108b via through-hole connecting terminals 109a-1 and 109b-1, respectively. In a cross-sectional structure of a semiconductor integrated circuit device, individual wiring layers are insulated by interlayer insulating films, though they are not shown in FIG. 10, and conductor members filled in through holes formed by opening the interlayer insulating films are termed the through-hole connecting terminals.
In the present specification, the power supply lines and the ground lines are generally termed “voltage supply lines”.
The element power supply lines 106a, the element ground lines 106b, the branch power supply lines 108a, and the branch grounded lines 108b each extending laterally in FIG. 10 are provided in a certain wiring layer. On the other hand, the trunk power supply lines 107a and the trunk ground lines 107b are provided in another wiring layer. The semiconductor integrated circuit device is provided on a semiconductor chip having power supply pads and ground pads to be connected to the branch power supply lines 108a and the branch ground lines 108b, respectively. The power supply pads and the ground pads are provided in the uppermost layer of the semiconductor chip so that the semiconductor integrated circuit device is electrically connectable to a power supply line and to a ground supply line each external of the semiconductor chip via the power supply pads and the ground pads.
Thus, in the state shown in a plan view, the element power supply lines 106a and the element ground lines 106b provided in the same wiring layer and extending laterally intersect the trunk power supply lines 107a and the trunk ground lines 107b provided in the other wiring layer and extending vertically. At the points of intersection of the power supply lines 106a and the trunk power supply lines 107a, the power supply lines 106a and the trunk power supply lines 107a are connected to each other via through-hole connecting terminals 109a-2. On the other hand, the ground lines 106b and the trunk ground lines 107b are connected to each other via through-hole connecting terminals 109b-2 at the points of intersection of the ground lines 106b and the trunk ground lines 107b. 
Thus, each of the wiring layer is internally provided with the plurality of lines extending in a specified direction. Since the through-hole connecting terminals are provided as required at the points of intersection of the lines contained in the different wiring layers, lines other than those shown in FIG. 10 should be placed with consideration. When signal lines, e.g., are placed in the individual wiring layers, the signal lines should be placed while avoiding the points of intersection.
However, the wiring structure in the conventional semiconductor integrated circuit device has the following drawbacks.
In the conventional structure, the points of intersection restrict the flexibility with which the signal lines are placed. It will be understood that the area allocated to the signal lines is reduced by the points of intersection. Moreover, the branch power supply lines 108a and the branch ground lines 108b are provided in the same wiring layer (first wiring layer) and the element power supply lines 106a of the cells and the element ground lines 106b thereof are also provided in the same wiring layer (first wiring layer). As a result, the cell rows 105x cannot be placed immediately below the branch power supply lines 108a and the branch ground lines 108b. This is because, under such a placement condition, the element power supply lines 106a of the cell rows 105x and the element ground lines 106b thereof are in contact with the branch power supply lines 108a and the branch ground lines 108b so that each of the element power supply lines 106a and the element ground lines 106b is short-circuited. In short, a portion of the cell placement region corresponding to the area occupied by the branch power supply lines 108a and the branch ground lines 108b is lost.
Thus, the conventional wiring structure is suitable for use in a semiconductor chip in which a fewer types of element circuits, such as a single digital circuit or a single SRAM (static random access memory), are integrated. In that case, the number of wiring layers is generally on the order of two. Since the number of wiring layers is small, an emphasis has been placed conventionally on the provision of an area for a region required for the signal lines.
However, the advent of a semiconductor chip having a plurality of circuits including a digital circuit, a SRAM, a DRAM (dynamic random access memory), a flash memory, and an analog circuit merged therein is expected in the future. Moreover, improvements in process technology allow miniaturization of elements in a semiconductor integrated circuit device so that an increase in the degree of integration of the digital circuit is also expected.
Therefore, the future trend in a semiconductor integrated circuit device is inevitably toward a larger wiring area required for the voltage supply lines of the individual element circuits and for signal lines and toward a larger number of wiring layers. The probability is higher that, in near future, a semiconductor integrated circuit device having, e.g., about six to ten wiring layers will be a main stream. As a transistor has been miniaturized increasingly by the improvements in process technology, a reduction in the power supply voltage of the transistor has been required not only in terms of lowering power consumption but also ensuring smooth operation of the transistor.
In a semiconductor integrated circuit device with a lower power supply voltage, allowance for voltage drop in the voltage supply lines is lowered. This is because, e.g., a slight reduction in power supply voltage causes a significant reduction in the operating speed of a transistor in the circuit. Accordingly, stricter restrictions will be placed on a drop in power supply voltage during the operation of the circuit in a future semiconductor integrated circuit device. Of the voltage drop, a drop (IR drop) resulting from the resistance of wiring accounts for a large proportion so that it is necessary to reduce the wiring resistance of the voltage supply lines. In the signal lines also, it is effective to reduce the resistance in minimizing signal delay. To reduce the wiring resistance, it is necessary not only to select a material for the wiring but also to increase the wiring area or the like. In increasing an area occupied by the voltage supply lines, an increase in the number of wiring layers and an increase in line width are effective. However, it is highly probable that an increased number of wiring layers increases fabrication cost for the integrated circuit device. On the other hand, an increased number of voltage supply lines reduces a space in which signal lines are placed accordingly.
Thus, a mere increase in the total area occupied by the voltage supply lines may cause increased fabrication cost or a degraded characteristic such as signal delay.
The power supply lines in the semiconductor integrated circuit device also have the drawback of causing the detriment of electromagnetic interference noise, which is generally termed EMI. In terms of product quality control, there is a stringent request on the electromagnetic interference noise that it should be smaller than a publicly determined minimum amount. It is known that the electromagnetic interference noise is caused by an inductance resulting from a time-varying change of a current flowing in the portion of a through-hole connecting terminal (e.g., a lead of a package or a wire) for providing a connection between the semiconductor integrated circuit device or the like and an external terminal. As a method for suppressing the electromagnetic interference noise, there is one which provides a capacitance between the power supply and the ground. However, the provision of the capacitance which requires a large area causes the drawback that an area for the cells and lines is reduced.
Hence, the power supply lines and the ground lines in future semiconductor integrated circuit devices should have structures which eliminate the foregoing drawbacks.
There is also a serious problem associated with an increase in the number of through-hole connecting terminals and the miniaturization thereof in future semiconductor integrated circuits, which are entailed by the merging of various types of circuits therein and the resultingly complicated structures thereof. The increased number of through-hole connecting terminals that have been miniaturized may significantly increase the probability of faulty connecting states. The faulty connecting states cause not only unexpected voltage drop but also maloperation of the entire circuit due to the current density in wiring which is increased locally. To prevent these, there is a growing demand on means for easily testing the connecting states at the through-hole connecting terminals.
In particular, a connected or unconnected state at a through-hole connecting terminal for providing a connection between lines each contained in a voltage supply wiring structure is related to whether or not an amount of voltage drop has a design value. If the through-hole connecting terminal which should be connected is in the unconnected state, a current path is interrupted at the through-hole connecting terminal in the unconnected state so that the amount of voltage drop is higher than the design value.
If the area occupied by the voltage supply lines is minimized, the width of each of the lines is reduced and the number of the through-hole connecting terminals is also reduced so that a current density in the lines approaches a permissible value and a design margin is reduced. The same shall apply to a current density at the through-hole connecting terminal. In addition, the through-hole connecting terminals in the semiconductor integrated circuit device are expected to be miniaturized in future, similarly to the other components thereof. As the through-hole connecting terminals are miniaturized increasingly, there should be a growing need to guarantee the connected states at the through-hole connecting terminals.
In the case of bonding two semiconductor chips to each other to provide a connection therebetween or bonding a semiconductor chip to an integrated substrate named as a micro substrate containing voltage supply lines and signal lines necessary for the operation of the semiconductor chip to provide a connection therebetween, which is a technology of recent remark, the testing of the connecting states at the connecting terminals bonded to each other is absolutely necessary.